TTTC Header Image
TTTC's Electronic Broadcasting Service
ITSW Logo

14th International Test Synthesis Workshop (ITSW 2007)
March 5-7, 2007
El Tropicana Riverwalk Hotel
San Antonio, Texas, USA

http://www.tttc-itsw.org

CALL FOR PAPERS
Scope -- Author Information -- Committees

Scope

Theme: Testing a Design in its Natural Habitat

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.

As ITSW moves to its new habitat in San Antonio, Texas, this year’s workshop will focus on post-silicon chip quality. ITSW 2007 will look at all aspects of testing in its natural habitat such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No-Fault Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will also consider the usual papers in the area of Test Synthesis including, but not limited, to the following:

  • Register Transfer Level DFT
  • High-Level/Behavioral Test Synthesis
  • System-on-a-Chip (SoC) DFT
  • Memory and Logic BIST
  • Test Synthesis for Debug and Diagnosis
  • DFT for Mixed-Signal Circuits
  • Test Resource Partitioning
  • Functional Verification
  • Power and Noise-Aware Test
  • DFT for At-Speed Test
  • High-speed I/O test
  • Reducing the Cost of Test
  • Design for Manufacturing and Yield
  • Board and System Test
  • SER / Concurrent Error Detection
  • Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org.

Author Information

top
To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by January 12, 2007 via email. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.

For general information, contact:

Srinivas Patil, General Chair
Design Technology Solutions
Intel Corporation
Austin, TX 78746, U.S.A.
Email: GeneralChair@tttc-itsw.org
(ph) 512-732-3951, (fax) 512-732-3912

Submit paper proposals to:

Jennifer Dworak, Program Chair
Division of Engineering
Brown University
Providence, RI, 02912, U.S.A.
Email:ProgramChair@tttc-itsw.org
(ph) 401-863-1531, (fax)401-863-9039

Committees

top

General Chair
S. Patil - Intel

Past General Chair
I. Harris - UC Irvine

Vice Chair
N. Mukherjee - Mentor G.

Program Chair
J. Dworak - Brown U.

Panels Chair
L. C. Wang - UC SB

Publicity Chair
V. Chickermane - Cadence

Finance Chair
N. Touba - U. Texas, Austin

Local Arrangements Chair
C. Barnhart - Silicon Aid

European Liaison
M. Zwolinski - U. Southampton

Asian Liaison
C. W. Wu - Nat. Tsing Hua U.

Program Committee
M. Abadir - FreeScale
R. Aitken - ARM
S. Blanton - Carnegie Mellon U.
D. Burek - Magma
K. Chakrabarty - Duke U.
K.-T.Cheng - UC SB
A. Crouch - Inovys
S. Davidson - Sun Micro.
D. Goswami - Mentor Graphics
M. Hsiao - Virginia Tech.
K. Iwasaki - Tokyo Metro. U.
A. Jas - Intel
R. Kapur - Synopsys
M. Laisne - QualComm
K.-J. Lee - Nat. Cheng-Kung U.
A. Majumdar - Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U. Texas
S. Oostdijk - Philips
A. Orailoglu - UC San Diego
S. Ozev - Duke U.
C. Papachristou - Case Western U.
J. H. Patel - U. Illinois
Z. Peng - Linkoping U.
B. Pouya - Freescale
D. K. Pradhan - Bristol
J. Rajski - Mentor Graphics
S. M. Reddy - U. Iowa
M. Sonza Reorda - Poli di Torino
M. Tahoori - Northeastern U.
S. Tragoudas - S. Illinois U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 14th International Test Synthesis Workshop (ITSW 2007) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Joan FIGUERAS
Universitat Politècnica de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Scott DAVIDSON
Sun Microsystems
- USA
Tel. +1-650-786-7256
E-mail scott.davidson@eng.sun.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies - France
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


This message contains public information only. You are invited to copy and distribute it further.

For more information contact the TTTC office or visit http://tab.computer.org/tttc/

To remove your name from this mailing list, please email unsubscribetttc@cemamerica.com or login to the TTTC Database and uncheck the EBS (Electronic Broadcast Service) box, which can modified by selecting "Edit" next to "My Subscriptions".